Key telephone system

ABSTRACT

A key telephone system is disclosed that includes a clock for generating both flash and wink lamp signals and digital timing signals. The system also includes a plurality of line control circuits, each of which is associated with an individual telephone line and a plurality of key telephone sets, each of which is associated with one or more telephone lines. Thus the key telephone systems includes a plurality of subsystems, each comprising a telephone line and the line circuit and elements of the key telephone sets associated with that telephone line. Each line circuit includes an electronic ringing detector and hold bridge circuit and a magnetic line current sensor. In addition, each line circuit includes several counters, and each counter is activatable to a plurality of states, one of which corresponds to a particular operational mode of the subsystem. A first group of logic gates responds to the occurrence of conditions associated with a particular operational mode (i.e., presence of loop current and absence of A lead current associated with hold mode) by applying the digital timing signals of the clock to one of the counters and/or enabling the counter to be advanced in response to such signals toward the state corresponding to that particular mode. A second group of logic gates respond to the counter reaching the corresponding state, indicating the continuous existence of the associated conditions for a predetermined period of time, by placing the subsystem in the particular mode (i.e., applying the hold bridge to the line and wink lamp signals to the sets).

This invention relates to the field of key telephone systems and withinthat field to an arrangement which lends itself to use in a smallbusiness environment.

BACKGROUND OF THE INVENTION

Most subscribers served by multiple telephone lines find that the basicfeatures that key telephone systems generally provide are quitedesirable. These features consist of (1) visual signaling for indicatingwhich of the lines is being rung, is in use, or on hold; (2) selectivepickup for enabling the use of any of the lines from a single set; and(3) selective application of a hold bridge for allowing a subscriberbusy on one line to hold the connection to that line and place orreceive a call on another line. It is clear that these features greatlyfacilitate efficient use of multiple telephone lines, and this hasresulted in widespread use of key telephone systems.

However, many small business subscribers whose needs are satisfied byfour telephone lines or less serving 20 stations or less find that thekey telephone systems presently available cost more than they wish tospend and/or require more space than they are able or willing to giveup. The problem to be solved therefore is the design of a key telephonesystem for such a small business environment that is less expensive thanexisting equipment and occupies a small amount of space.

My solution to this problem relies upon the use of electronic digitalcircuitry. The 60 Hertz power required to operate key telephone systemsprovides the basic timing function needed for such circuitry. Inaddition, such circuitry lends itself to integration which provideseconomies of both space and cost.

The use of digital circuitry in a key telephone system is disclosed inU.S. Pat. No. 3,604,857 issued to D. C. Opfermann, on Sept. 14, 1971.However, in that key telephone system, in addition to a line circuit ormodule being associated with each telephone line, a station module isassociated with each station set, interconnection therebetween beingaccomplished by crosspoint modules. Furthermore, each station set musttransmit and receive digital data signals and therefore special purposerather that standard station sets must be used.

Finally, in that key telephone system, clock pulses are used toestablish time slots, each of which is assigned a particular bit ofinformation. The bits of information are transmitted in a particularsequence between each line module and the associated station modules andbetween each station module and its associated station set. In additioneach line module is enabled in a particular sequence.

Each line module includes a 9 state counter and when a particular linemodule is enabled in its turn, the counter thereof is always steppedthrough all 9 states. The first 5 states serve to transmit informationbits to the associated station modules, 4 of the 5 states causingenabling pulses to be applied to individual transmit logic gates thatprovide unique outputs dependent upon information bits received from theassociated station modules during the previous advancement of thecounter. The sixth state causes an enabling pulse to be applied to theassociated crosspoint modules, while the last 3 states serve to receiveinformation bits from the associated station modules, these 3 statescausing enabling pulses to be applied to individual receive logic gatesthat provide unique outputs dependent upon information bits concurrentlyreceived from the associated station modules. The receive logic gatesserve to set or reset memory flip-flops that provide inputs to thetransmit logic gates during the next advancement of the counter.

SUMMARY OF THE INVENTION

A key telephone system in accordance with the present invention is offar greater simplicity. No station modules or crosspoint modules arerequired, and standard key telephone sets may be used. Furthermore,rather than continuously scanning the components of the system todetermine whether conditions have changed, the system responds only whena change in conditions occurs and remains essentially quiescent duringother times.

The key telephone system disclosed herein includes a clock forgenerating both flash and wink lamp signals and digital timing signals.The system also includes a plurality of line control circuits, each ofwhich is associated with an individual telephone line and a plurality ofkey telephone sets, each of which is associated with one or moretelephone lines. Thus the key telephone system includes a plurality ofsubsystems, each comprising a telephone line and the line circuit andelements of the key telephone sets associated with that telephone line.Each line circuit includes an electronic ring detector and hold bridgecircuit and a magnetic line current sensor. In addition, each linecircuit includes several counters. Each counter is activatable to aplurality of states, one of which corresponds to a particularoperational mode (i.e., idle, hold) of the subsystem.

A first group of logic gates responds to the occurrence of conditionsassociated with a particular operational mode (i.e., presence of linecurrent and absence of A lead current associated with hold mode) byapplying the digital timing signals of the clock to one of the countersand/or enabling the counter to be advanced in response to such signalstoward the state corresponding to that particular mode. A second groupof logic gates responds to the counter reaching that correspondingstate, indicating the continuous existence of the associated conditionsfor a predetermined period of time, by placing the subsystem in theparticular mode (i.e., apply wink lamp signals to the sets at the sametime that the hold bridge is applied to the associated telephone line).

DESCRIPTION OF THE DRAWING

FIG. 1 is a sketch showing the components of a key telephone system inaccordance with the invention;

FIGS. 2 through 5 present a schematic circuit diagram of the keytelephone system;

FIG. 6 is a block diagram showing the arrangement of FIGS. 2 through 5;and

FIG. 7 is a timing plot of signals generated by the clock of the keytelephone system.

DETAILED DESCRIPTION OF THE INVENTION

In the description that follows, the first digit of the reference numberof each component refers to the drawing figure number where thatcomponent is shown.

Referring to FIG. 1, a key telephone system for a small businessenvironment in accordance with the present invention includes aplurality of standard telephone sets, such as found in existing keytelephone systems. The telephones may be either key telephones or singleline sets. Furthermore, since no dial register is required in the keytelephone system of this invention, the telephones may be a mixture ofrotary and pushbutton dial sets. Three sets are shown, a rotary dialsingle line set 201, a pushbutton dial key set 202, and a rotary dialkey set 302.

With the use of such standard telephone sets, the circuitry of the keytelephone system is housed within a controller unit 100. Alternatively,the circuitry could be housed within one or more special purpose sets. Amulticonductor cable 110 connects a plurality of central officetelephone lines to the controller unit 100 and connects the circuitry ofthe controller unit to each of the telephone sets. Bridging adapters 115are advantageously used to interconnect the controller unit 100 witheach of the sets.

All of the telephones are wired identically, that is, the correspondingbutton in each key set has the same function or telephone lineassociated therewith. Thus, the first button in each key set is the holdbutton HO, the second button in each set is the pickup button PU1 forline 1, the third button in each set is the pickup button PU2 for line2, and so on. As a result, the interconnecting cable 110 is the sameeverywhere in the system, eliminating the need for a cross connectfield, and the cable may be either connector ended or cut down dependingupon the need of the installation.

Referring now to FIGS. 2, 3, 4, and 5, which are arranged in accordancewith FIG. 6, the key telephone system shown services two telephone linesTL1 and TL2 and the three telephone sets 201, 202, and 302 and includesa pair of line control circuits LCC1 and LCC2. The telephone line TL1 isassociated with the line control circuit LCC1 and elements of thetelephone sets 201, 202 and 302, and this combination comprises asubsystem of the key telephone system. Similarly, the telephone line TL2is associated with the line control circuit LCC2 and elements of thetelephone set 202 and 302, and this combination comprises anothersubsystem of the key telephone system. Both subsystems have a pluralityof operational modes, i.e., idle, ringing, in-use, and hold, and eachsubsystem can be in a different operational mode.

The line control circuits LCC1 and LCC2 are identical and therefore onlyone line control circuit, in this case LCC1, need be described indetail. The major components of the line control circuit LCC1 comprise ahold bridge circuit 220, a line current sensor 240, a ringing detector260, and a logic circuit 400, the logic circuit including a serviceflip-flop 410, a data latch 415, a hold counter 420, a hold releasecounter 425, and a ringing flash counter 430. The details of thesecomponents will be described with respect to the operation of theassociated subsystem.

In addition to the foregoing the key telephone system includes a powersupply 310 and a clock 500. The power supply 310 is connected to astandard 110 volt, 60 cycle source, such as by a plug ended power cord312, and includes a transformer 314 from which is derived 13 volt ac forilluminating the lamps of the key sets. Negative half cycle ac isapplied to the lamps via conductor 315 connected to what is commonlyreferred to as the A lead and what is herein referred to as the signallead A of each set, while positive half cycle ac is applied to the lampsvia conductors 316, 501, and a silicon controlled rectifier in each linecircuit which is connected to the associated lamp lead L of each keyset. The output of the transformer 314 is also rectified and applied toa voltage regulator 320 to provide well regulated 5 volt dc power neededfor the operation of both the clock 500 and the line control circuits.

The clock 500 relies upon the 60 cycle ac commercial power frequency asa timing reference from which all system clocking information isderived. The clock 500 includes transistors 510, 512, and 514 whichrespectively provide three squared-off and phase-shifted signals deriveddirectly from the secondary of the transformer 314 of the power supply310. The output of transistor 510 provides a service clock signal SCLK,shown in FIG. 7, that is applied to the service flip-flop in each linecontrol circuit. The output of transistor 512 provides a 270°phase-shifted signal input to a monostable multivibrator 520, which inturn provides a line clock signal LCLK, shown in FIG. 7, that is appliedto the line current sensor in each line control circuit. The output oftransistor 514 provides a 180° phase-shifted signal input to both amonostable multivibrator 525 and a divide by 3 counter 530. Themonostable multivibrator 525 provides a data clock signal DCLK, shown inFIG. 7, that is applied to the data latch in each line control circuit,while the divide by 3 counter 530 provides a 20 Hertz counter clocksignal CCLK, shown in FIG. 7, used as one of the gate inputs to advancethe hold release counter in each line control circuit.

The 20 Hertz output of the divide by 3 counter 530 also serves as aninput to a 4 bit decade counter 535, and the A and D outputs of thecounter are connected to a NAND gate 540 that provides a 2 Hertz winkclock signal WCLK having the proper timing (450 msec at 1 and 50 msec at0) to control the lamp wink rate in accordance with generally acceptedstandards. Finally, the 2 Hertz output of the gate 540 is also appliedto a divide by 2 counter 545, the output of which provides a 1 Hertzflash clock signal FCLK having the proper timing (500 msec at 1 and 500msec at 0) to control the lamp flash rate in accordance with generallyaccepted standards.

With this background we shall now describe the operation of thesubsystem including line control circuit LCC1 in each of the variousoperational modes of the subsystem, that is, idle, ringing, in-use, andhold. When reference is made to the input leads of gates the numberingis from top to bottom or from left to right as the case may be.

IDLE MODE

When the subsystem is in the idle operational mode, the telephone set210 is on hook, and the telephone sets 202 and 302 are either on hook orthe line pickup buttons PU1 thereof are unoperated whereby the contactsof PU1 are open. Therefore the negative half cycle ac applied by thepower supply 310 to the signal leads A of the sets is not connectedeither to the lamps LP1 of the sets 202 and 302 or to the emitter oftransistor 435 of line control circuit LCC1. As a result of the former,the lamps LP1 are not illuminated. As a result of the latter, transistor435 is turned off, whereby its collector rides high. This places a 1 oninput lead S of the service flip-flop 410, and since the flip-flop isheld in the reset condition, the service clock signal SCLK, shown inFIG. 7, applied to input lead R of the flip-flop has no effect at thistime.

The output Q of the service flip-flop 410 places a 0 on the input lead Dof the data latch 415. Because the output Q of the data latch 15 isdetermined by the signal on the input lead D at the time a pulse isapplied to the strobe input lead ST, the strobe pulse in this case beingthe data clock signal DCLK shown in FIG. 7, the output Q in the idlemode is 0. The output Q of the data latch 415 is the inverse of Q.

In addition, for reasons that will become clear as the descriptionproceeds, when the subsystem is in the idle mode, the hold counter 420,which is a 2 bit binary counter, is at 0, 1, or 2 count. Therefore, a 0is applied to either one or both output leads A and B of the holdcounter 420. A NAND detector gate 440 connected to the A and B outputleads consequently applies a 1 to an inverter 442, which in turn appliesa 0 to the first input lead of a NAND wink gate 444. The wink gate 444is thereby disabled, and the wink clock signal WCLK applied to thesecond input lead of the wink gate does not pass through the gate.

The hold release counter 425, which is a 4 bit decade counter, is at a 9count, and therefore a 1 is applied to both output leads A and Dthereof. A NAND detector gate 446 connected to the A and D output leadsthereby applies a 0 to the first input lead of a NAND counter input gate448. As a result, the counter input gate 448 is disabled and the counterclock signal CCLK applied to the second input of the gate does notadvance the counter.

Furthermore, the ringing flash counter 430, which is also a 4 bit decadecounter is also at a 9 count. The 1 appearing at output leads A and Dthereof is applied to a NAND detector gate 450 which in turn applies a 0to the second input lead of a NAND flash gate 452. Thus, the flash gate452 is disabled and the flash clock signal FCLK applied to the firstinput lead of the gate does not pass through the gate.

It is seen that the outputs of the wink gate 444 and the flash gate 452,which are both at 1 in the idle mode, serve as the inputs to a NAND lampdriver gate 454, the output of which is connected to the gate lead oflamp control SCR 401. The SCR 401 is turned on by a 1 output from thelamp driver gate 454 to apply positive half cycle ac to the lamps LP1 ofthe telephone sets 202 and 302, and since the output of the lamp drivergate in the idle mode is 0, the lamps are not illuminated in accordancewith either the flash clock signal FCLK or wink clock signal WCLK.

Finally, in the idle mode the line clock signal LCLK does not passthrough the line current sensor 240. As indicated by the schematicdrawing of the line current sensor 240, it comprises a closed magneticcore 242 having three parallel legs. Sense windings 244 and 245, towhich the line clock signal LCLK is connected, are disposed about theouter legs. In addition, the sense windings 244 and 245 have the samenumber of turns, are connected in series with one another, and are poledoppositely to one another. Control winding 246, which is connected inseries with the tip conductor of the telephone line, is disposed aboutthe center leg of the magnetic core 242. The number of turns in each ofthe windings and the dimensions of the magnetic core are selected sothat line clock signals LCLK applied to the sense windings 244 and 245when no line current is flowing through the control winding 246 resultsin no signals being induced in the control winding and no signals beingpassed through the sense windings. This is because the structureprovides a high inductance that essentially extinguishes the signals.When, however, line current of either polarity is present, the fluxgenerated by the control winding 246 saturates the magnetic core,significantly reducing the inductance of the structure, and line clocksignals LCLK pass through the sense windings 244 and 245.

RINGING MODE

When ringing voltage is applied to the telephone line TL1, it appearsacross the ringers RG1 of each of the telephone sets 201, 202 and 302.Thus all three sets are rung. In addition, the ringing voltage isapplied to capacitor 262 and primary winding 264 of transformer 265 ofthe ringing detector 260. A voltage is thereby induced in secondarywinding 266 of the transformer 265 that is rectified and filtered, andafter several cycles of 20 Hertz ringing, transistor 268 is turned on.

The turning on of transistor 268 applies a 1 to reset input lead R ofthe ringing flash counter 430 and the counter is reset to 0 count,whereby a 0 is applied to both output leads A and D of the counter. Thedetector gate 450 consequently applies a 1 to the second input lead ofthe flash gate 452, and the gate is enabled to apply the flash clocksignal FCLK (500 msec at 1 and 500 msec at 0) to the second input leadof the lamp driver gate 454. Since the first input lead of the lampdriver gate 454 has a 1 applied thereto by the wink gate 444, the lampdriver gate applies the flash clock signal FCLK to the lamp control SCR401. The lamp control SCR 401 is turned on and off in accordance withthe flash clock signal FCLK, and when turned on it applies positive halfcycle ac to the lamps LP1 of telephone sets 202 and 302 via theconductor 210 and lamp lead L1. The lamps LP1 consequently flash on andoff to provide a visual signal for indicating ringing on telephone lineTL1 and the subsystem is placed in the ringing mode.

Anytime the ringing signal is removed from the telephone line TL1, whichoccurs either to provide the silent interval between ringing signals orbecause the calling party has hung up, the transistor 268 of the ringingdetector 260 turns off. A 0 is then applied to the reset lead R of theringing flash counter 430, and the counter is no longer held in a resetcondition. It is seen that the flash gate 452, in addition to applyingthe flash clock signal FCLK to the lamp driver gate 454, also appliesthis signal to input lead IN of the ringing flash counter 430. Thus whenthe reset signal is removed, the flash clock signal FCLK commences toadvance the ringing flash counter 430 at a 1 Hertz rate.

Inasmuch as the ringing flash counter 430 is a 4 bit decade counter, oneor the other of the output leads A and D is a 0 through the count of 8.Thus throughout that count, the output of the detector gate 450 remainsa 1 and the flash gate 452 is enabled to respond to the flash clocksignal FCLK. Since the silent interval between each ringing signal istypically only 4 seconds in duration, the approximately 9 secondsrequired to advance the ringing flash counter 430 beyond the count of 8provides more than enough time to span the silent intervals betweenringing signals.

If the ringing signal has stopped to provide the silent interval betweenringing signals, then when the next ringing signal occurs, thetransistor 268 of the ringing detector 260 is again turned on, andringing flash counter 430 is again reset to 0. Thus the counter beginscounting from 0 at the beginning of each silent interval.

If, on the other hand, the ringing signal has stopped because thecalling party has hung up, then the ringing flash counter 430 willadvance until it reaches the count of 9. At this count a 1 is applied toboth output leads A and D, causing the detector gate 450 to apply a 0 tothe second input lead of the flash gate 452. The flash gate 452 isthereby disabled, terminating both the flashing of the lamps LP1 of thetelephone sets 202 and 302, and the pulsing of the input lead 1N of theringing flash counter 430. The ringing flash counter 430 remains at thecount of 9 and the subsystem is returned to the idle mode.

IN-USE MODE

When the telephone set 201 goes off hook or when either telephone set202 or 302 goes off hook with the pickup button PU1 operated, thetelephone line TL1 is seized. Assuming, for example, that telephone set302 has gone off hook with its pickup button PU1 operated, wherebyswitch hook contacts SH and pickup contacts PUT1, PUR1, and PUA1 are allclosed, a path is provided from the central office or local PBX on tiplead T1 into the line control circuit LCC1, through control winding 246of the line current sensor 240, back out from the line control circuitto the telephone set 302, through closed pickup contacts PUT1 and closedswitch hook contacts SH to the speech network SN of the telephone set,and back out from the telephone set through closed pickup contacts PUR1to the ring lead R1 to return to the central office or local PBX. Thusthe speech network SN of the telephone set 302 is connected across thetelephone line TL1.

As described above, the presence of line current on the control winding246 of the line current sensor 240 permits the line clock signals LCLKto pass through the sensor. This signal is applied to the reset input Rof the hold release counter 425. Thus when the telephone line TL1 isseized, the hold release counter 425 is reset to the 0 count, whereby 0is applied to both output leads A and D thereof. As a result, thedetector gate 446 applies a 1 to the second input lead of NAND resetgate 422 and the first input lead of counter input gate 448. The resetgate 422 is thereby enabled to respond to the output Q of the serviceflip-flop 410 while the counter input gate 448 is enabled to respond tothe counter clock signal CCLK.

At the same time, a path is completed from the power supply 310 whichapplies negative half cycle ac through conductor 315, the signal lead A,the closed switch hook contacts SH, the closed hold contacts HO, and theclosed pickup contacts PUA1 to lamp lead L1. From the lamp lead L1 thenegative half cycle ac power extends to lamp LP1 and lamp ground LG inboth the telephone sets 202 and 302 whereby the lamps LP1 in both setsare provided steady illumination to indicate that the telephone line TL1is in use.

In addition, the negative half cycle ac power from the lamp lead L1extends to the line control circuit LCC1 wherein a path is provided toground via conductor 210 and resistors 404 and 405. The presence ofnegative half cycle ac at the emitter of the transistor 435 causes it toturn on during each negative half cycle. Each time it turns on, itapplies a 0 to the input lead S of the service flip-flop 410, and sinceas shown in FIG. 7, the service clock signal SCLK applies a 1 to inputlead R during each negative half cycle, the flip-flop is placed in a setcondition during this phase of each cycle. In the set condition, theoutput Q goes to 1 and the output Q goes to 0. Then during each positivehalf cycle when the transistor 435 turns off, a 1 is again applied tothe input lead S and the service clock signal SCLK applies a 0 to theinput lead R to reset the service flip-flop 410, whereby the output Qgoes to 0 and the output Q goes to 1.

The output Q of the service flip-flop 410 is applied to input lead D ofthe data latch 415. Because as shown in FIG. 7, the data latch 415 isstrobed by the data clock signal DCLK prior to the service clock signalSCLK applying a 0 to the reset input lead R of the service flip-flop430, a 1 is applied to output Q of the data latch the first time theflip-flop is set and this output remains at a 1 as long as the flip-flopcontinues to be periodically set by the negative half cycle ac power onthe signal lead A.

The 0 provided on output lead Q of the data latch 415 is applied to thesecond input lead of NAND preset gate 456 whereby a 1 is applied to thepreset input P of the ringing flash counter 430. This causes the counterto be preset to and/or held at the 9 count. Thus if the subsystem hadbeen in the ringing mode when telephone line TL1 was picked up, thepresetting of the ringing flash counter 430 to the 9 count wouldimmediately disable the flash gate 452 and thereby terminate theapplication of positive half cycle ac at the flashing rate to the lampsLP1 of the telephone sets 202 and 302.

The first time that the service flip-flop 410 is set, the 0 on the Qoutput is applied to the first input lead of the reset gate 422 wherebya 1 is applied to the reset input lead R of the hold counter 420. Thiscauses the counter to be est to and/or held at the 0 count. Thus if thesubsystem had been in the hold mode when the telephone line TL1 waspicked up, the resetting of the hold counter 420 to the 0 count wouldimmediately disable the wink gate 444 and thereby terminate theapplication of positive half cycle ac at the winking rate to the lampsLP1 of the telephone sets.

With the hold counter 420 at the 0 count, the A and B output leadsthereof both have a 0 applied thereto. It is seen that the A and Boutput leads, in addition to being connected to the detector gate 440,are respectively connected to the first and second input leads of NORdetector gate 416, the third input lead of which is connected to the Qoutput of the data latch 415. Thus with negative half cycle ac presenton the signal lead A whereby the output Q of the data latch 415 is at 1,the output of the detector gate 416 is a 0. This is changed to a 1 byinverter 418 and applied to the first input lead of NAND counter inputgate 424. The fourth input lead of the counter input gate 424 isconnected to the output of the detector gate 440 and with the holdcounter 420 in the 0 count this output is a 1. The third input lead ofthe counter input gate 424 is connected to the output Q of the serviceflip-flop 410, while the second input lead is connected to the sensewindings 244 and 245 of the line current sensor 240.

HOLD MODE

To place the telephone line TL1 on hold, the hold button HO (FIG. 1) isoperated whereby the hold contacts HO (FIG. 3) are opened. The negativehalf cycle ac on the signal lead A and the lamp lead L1 is therebyinterrupted, turning the lamps LP1 and the transistor 435 off. The next0 input of the service clock signal SCLK to the input R of the serviceflip-flop 410 resets the flip-flop and it remains in the reset conditionas long as transistor 435 stays off. The output Q of the serviceflip-flop 410 goes to a 0 while the output Q goes to a 1. Since as shownin FIG. 7, the data clock signal DCLK strobe pulse applied to the datalatch 15 precedes the resetting pulse of the service clock signal SCLK,the data latch output momentarily remains the same.

Consequently, the 1 on the Q output of the service flip-flop 410 appliedto the third input lead of the counter input gate 424 in addition to the1 already present on the first and fourth input leads thereof enablesthe gate to respond to the 60 Hertz line clock signal LCLK which,because line current is still present, is passed through the linecurrent sensor 240 and applied to the second input lead of the gate. Asshown in FIG. 7, the pulse of the line clock signal LCLK is in betweenthe resetting pulse of the service clock signal SCLK and the strobepulse of the data clock signal DCLK. Therefore, the first line clockpulse LCLK occurring after the service flip-flop 410 has been resetapplies a 0 to input lead 1N of the holder counter 420 and advances thecounter to the first count. At this count, a 1 is applied to output Aand a 0 is applied to output B. Thus output of detector gate 440 remainsa 1 while the output of detector gate 416 remains a 0. Furthermore, whenthe first pulse of the data clock signal DCLK following the resetting ofthe service flip-flop occurs, whereby the output Q of the data latch 415goes to 0, the detector gate 416 still provides a 0 output.

On the third pulse of the line clock signal LCLK, which occurs between36 and 52 msec after the hold contacts HO are opened, the counter isadvanced to the third count wherein a 1 is applied to both output leadsA and B thereof. The output of the detector gate 440 thereupon goes to 0thereby disabling the counter input gate 424 and leaving the holdcounter 420 in the third count. In addition, the 0 output of thedetector gate 440 is changed to a 1 by the inverter 442 to enable thewink gate 444 to apply the wink clock signal WCLK (450 msec at 1 and 50msec at 0) to the first input lead of the lamp driver gate 454. Sincethe second input lead of the lamp driver gate 454 has a 1 appliedthereto by the flash gate 452, the lamp driver gate applies the winkclock signal WCLK to the lamp control SCR 401. The lamp control SCR 401is thereby turned on and off in accordance with the wink clock signalWCLK, and when turned on it applies positive half cycle ac to the lampsLP1 of the telephone sets 202 and 302 via the conductor 210 and the lamplead L1. The lamps LP1 consequently wink on and off to provide a visualsignal for indicating that the telephone line TL1 is on hold.

The output from the inverter gate 442 is also applied through a resistor222 and a winding 224 of a transformer 225 to the base of a transistor226 of the hold bridge circuit 220. The transformer 225 and transistor226 form a simple oscillator that is turned on by the 1 output from theinverter gate 442. A voltage is thereby induced in winding 228 of thetransformer 225 that is rectified and filtered and used to bias ontransistors 230 and 232. The transistors 230 and 232 are of the highvoltage type so as to withstand dial pulsing and high voltage transientson the telephone line. In addition the transistors 230 and 232 arearranged with blocking diodes 234 and 235 so that a bridging path isprovided across the telephone line TL1 regardless of the polarity of theline current. Furthermore the bridging path includes a winding 236 onthe ringing transformer 265 shunted by a resistor 238. This combinationprovides a hold bridge path having approximately the same ac and dcimpedance as the speech network of a telephone set.

Thus it is seen that when the hold counter 420 advances to the count of3, a winking signal is applied to the line lamp LP1 of the telephonesets 202 and 302 and a hold bridge is applied across the telephone lineTL1. The hold button HO of the telephone set 302 is thereafter releasedwhereby the hold contacts HO reclose and the pickup button PU1 ismechanically released to open pickup contacts PUT1, PUR1, and PUA1. Theopen pickup contacts PUT1 and PUR1 remove the speech network SN of thetelpehone set 302 from across the telephone line TL1 while the openpickup contacts PUA1 continue to disconnect negative half cycle ac fromthe lamp lead L1. Consequently, the line lamp LP1 is only illuminatedresponsive to the wink clock signal WCLK. The subsystem is therebyplaced in the hold mode.

It should be noted that is possible to advance the hold counter 420 1 or2 counts following going on hook from the in-use mode if a large numberof ringers are bridged on the telephone line TL1. The current flow whilethe capacitors of the ringers are being charged is interpreted by theline current sensor 240 as the continued presence of line current. Forthis reason line current must persist long enough to advance the holdcounter 420 to the third count in order to place the subsystem in thehold mode, and this is a greater length of time than will result fromringer capacitor charging following the going on hook.

Should the party on hold abandon the call, modern central offices dropthe connection to the line whereby line current is terminated. However,interruption of line current of 300 msec or less occurs in some centraloffices during the normal processing of telephone calls. Thus it isnecessary to distinguish between central office cutoff of an abandonedcall and normal processing.

When line current on the telephone line TL1 is interrupted, current flowthrough the control winding 246 of the line current sensor 240 isterminated. As a result, the line clock signal LCLK is no longer passedthrough the sense windings 244 and 245 and pulsing of the input lead Rof the hold release counter 425 ceases. Since the hold release counter425 is no longer being reset to a 0 count by the line clock signal LCLK,it now advances responsive to the 20 Hertz counter clock signal CCLKapplied to the second input lead of the counter input gate 448.

Inasmuch as the hold release counter 425 is a 4 bit decade counter, oneor the other of the output leads A and D is a 0 through the count of 8.Consequently, until the hold release counter 25 reaches the count of 9,which at a 20 Hertz pulsing rate requires approximately 450 msec, theoutput of the detector gate 446 remains at 1, and the counter input gate448 remains enabled to respond to the counter clock signal CCLK. Shouldthe interruption of the line current be due to something other thancentral office cutoff, line current will be reestablished before 450msec have expired. As soon as line current is again present on thecontrol winding 246 of the line current sensor 240, the line controlsignal LCLK is passed through the sense windings 244 and 245 to thereset input lead R of the hold release counter 425 and the counter isreset to the 0 count.

If on the other hand, central office cutoff has occurred, then the holdrelease counter will advance to the count of 9, whereupon a 1 is appliedto both output leads A and D thereof. The output of the detector gate446 then goes to 0, disabling the counter input 448 and leaving the holdrelease counter at a count of 9. In addition, the 0 output of thedetector gate 446 is applied to the second input lead of reset gate 442whereby the reset gate applies a 1 to the reset input lead R of the holdcounter 420 to reset the counter to the 0 count. The output of thedetector gate 440 thereupon goes to 1 which is changed to a 0 by theinverter 442. This 0 output of the inverter 442 terminates the operationof the oscillator comprising the transistor 225 and transformer 226 ofthe hold bridge circuit 220 and thereby removes the hold bridge fromacross the telephone line TL1. Furthermore, the 0 output of the inverter442 disables the wink gate 444 whereby winking of the lamps LP1 of thetelephone sets 202 and 302 is terminated and the subsystem is returnedto the idle mode.

Although a specific embodiment of the invention has been shown anddescribed, it will be understood that it is but illustrative and thatvarious modifications may be made therein without departing from thescope and spirit of this invention as defined in the appended claims.

What is claimed is: .[.1. A telephone line control circuit for use in atelephone system comprising a telephone line, the line control circuit,and at least one telephone set associated with the telephone line, thesystem having a plurality of operational modes, the line circuitcomprising: lamp..].
 8. A control circuit .[.as in claim 7 wherein.]..Iadd.for use in a telephone system comprising a telephone line, thecontrol circuit, and at least one telephone set including a ringer and asignal lamp, the system having operational modes of idle, ringing,in-use, and hold, the ringing mode being characterized by flashing ofthe signal lamp and periodic operation of the ringer responsive to theperiodic application of ringing voltage to the telephone line, thecontrol circuit comprising:counter means activatable to a plurality ofstates, one of which corresponds to the idle mode; means responsive tothe cessation of ringing voltage for a continuous period of timeexceeding the time period of the silent intervals between eachapplication of ringing voltage for advancing the counter means to thestate corresponding to the idle mode; and idle mode logic meansresponsive to the counter means advancing to said corresponding statefor terminating the flashing of the signal lamps, .Iaddend.the idle modelogic means .[.comprises.]. .Iadd.comprising .Iaddend.a first logic gatethat has a unique output only in response to the counter means advancingto said corresponding state, the unique output serving to disable asecond logic gate having as one of its inputs a clock signal thatprovides the timing of the flashing of the signal lamp.
 9. A controlcircuit .[.as in claim 1 wherein the.]. .Iadd.for use in a telephone.Iaddend.system .[.has.]. .Iadd.having .Iaddend.operational modes ofidle, ringing, in-use, and hold .[.and the set includes.]..Iadd., thetelephone system comprising a telephone line, the control circuit, andat least one telephone set including .Iaddend.a signal lead, a speechnetwork, and switch hook contacts for connecting the speech network tothe associated telephone line, current being present on both the signallead and the associated telephone line when the system is in the in-usemode, and the signal lead being interrupted when the system is to beplaced in the hold mode, .[.and wherein the condition responsive meansincludes.]. .Iadd.the control circuit comprising:counter meansactivatable to a plurality of states, one of which corresponds to thehold mode; .Iaddend. means responsive to the presence of line current onthe associated telephone line and the cessation of signal lead currentwhen the system is in the in-use mode for .[.advancing.]..Iadd.activating .Iaddend.the counter means.[...]. .Iadd.to advancetoward the corresponding state; and means responsive to the advancementof the counter means to the corresponding state for placing the systemin the hold mode. .Iaddend. A control circuit as in claim 9 wherein thecounter means is advanced to a state corresponding to the hold moderesponsive to the presence of line current and absence of signal leadcurrent for a continuous period of time exceeding the maximum timeperiod that line current continues after the speech network isdisconnected from the associated telephone line by the opening of theswitch hook contacts while the system is in the in-use mode.
 11. Acontrol circuit as in claim 10 wherein the counter responsive meansincludes hold mode logic means responsive to the counter means advancingto said corresponding state for applying a hold bridge to the associatedtelephone line that shunts the speech network of the set.
 12. A controlcircuit as in claim 11 wherein the telephone set further includes asignal lamp and the hold mode logic means initiates winking of thesignal lamp responsive to the counter means advancing to said selectedstate.
 13. A control circuit as in claim 12 wherein the hold mode logicmeans comprises a first logic gate having a unique output responsive tothe counter means advancing to said corresponding state, the uniqueoutput serving to apply the hold bridge and enable a second logic gatehaving as one of its inputs a clock signal that provides the timing ofthe winking of the signal lamp. .[.14. A control circuit as in claim 1wherein the system has operational modes of idle, ringing, in-use, andhold and wherein the condition responsive means includes meansresponsive to the cessation of line current on the associated telephoneline while the system is in the hold mode for advancing the countermeans..]. .[.15. A control circuit as in claim 14 wherein the linecurrent cessation means comprises means for detecting line current onthe associated telephone line, the line current detecting meansproviding a first logic signal when line current is present and a secondlogic signal when line current is absent, and logic means that activatesthe counter means responsive to the absence of the first logic signaland the presence of the second logic signal..]. .[.16. A control circuitas in claim 15 wherein the counter means is set at zero count responsiveto the first logic signal of the line current detecting means and thecounter activating logic means is permitted to advance the counter meansresponsive to the absence of the first logic signal and the presence ofthe second logic signal..]. .[.17. A control circuit as in claim 1wherein the telephone set includes a speech network and a signal lampand the system has operational modes of idle, ringing, in-use, and hold,the hold mode being characterized by winking of the signal lamp and thepresence of a bridging path across the associated telephone line thatshunts the speech network of the telephone set, and wherein the countermeans is advanced to a state corresponding to the idle mode responsiveto the termination of line current on the associated telephone line fora predetermined period of time while the set is in the hold mode..]..[.18. A control circuit as in claim 17 wherein the counter responsivemeans includes idle mode logic means responsive to the counter meansadvancing to said corresponding state for terminating the winking of thesignal lamp and removing the bridging path from across the associatedtelephone line..].
 19. A line circuit for a telephone system whichincludes a telephone line formed by a pair of line conductorsinterconnecting a central office with a telephone set, the telephone sethaving means for completing a path between the line conductors to permitline current to flow, the circuit comprising:a magnetic structure havingthree magnetic flux paths connected in parallel with one another; acontrol winding disposed about the middle magnetic flux path of themagnetic structure, the control winding being dimensioned so that theflux generated thereby when current the magnitude of the line currentflows therethrough saturates the magnetic structure; means forconnecting the control winding in series with one of the line conductorswhereby line current flows through the control winding when the linecurrent is present on the line conductors; a sense winding disposedabout each of the outer flux paths of the magnetic structure, the sensewindings both having approximately the same number of turns and beingpoled oppositely to and connected in series with one another; means forconnecting the input of the sense windings to a signal source; and meansconnected to the output of the sense winding for responding to thesignal of the signal source.
 20. In a line circuit for a telephonesystem which includes a telephone line formed by a pair of lineconductors interconnecting a central office with a telephone set, acircuit for applying a bridging path across the line conductors inparallel with the telephone set when the telephone line is placed onhold, the circuit comprising:a transformer having a first and secondwinding magnetically coupled to one another; an oscillator including thefirst winding of the transformer, the oscillator when turned ongenerating an ac voltage that is coupled to the second winding of thetransformer; means for rectifying the voltage induced in the secondwinding of the transformer; a transistor having its base connected tothe output of the rectifying means and its emitter-collector pathconnected in series with an impedance, the transistor being turned onresponsive to dc voltage provided by the rectifying means; and means forconnecting the emitter-collector impedance path across the lineconductors of the telephone line whereby when the oscillator is turnedon, the transistor is turned on and the impedance is connected acrossthe line conductors of the telephone line.